The present invention relates to a method and apparatus for providing dynamic early indications for a computer subsystem function that informs a processor to perform associated processing.
Computers typically include several subsystems that perform one or more predetermined or desired functions, such as functions associated with data transfer, communications, data processing, etc. It is often desired to inform a processor or central processing unit (CPU) of the computer to perform processing associated with one or more of the subsystem functions. In this manner, the subsystem cooperates with the CPU by completing a task or operation and informing the CPU of the completed task so that the CPU may perform further processing. For example, an expansion or adapter card may be plugged into a peripheral bus of a computer that transfers data to the main memory of the computer. The expansion card sends an interrupt to the CPU after the data is transferred, so that the CPU may execute an interrupt handling routine to process the data.
Significant delay may occur between the time the interrupt is asserted until the CPU begins the associated processing in response to the interrupt. Such delays may arise from several sources, such as from bus and logic latency while transferring the interrupt to interrupt handling logic, and/or from the CPU completing a current task and executing an interrupt service routine (ISR) or driver associated with the particular type of interrupt. Such delays cause inefficiency of the subsystem, which may affect the overall performance of the computer system.
One exemplary subsystem is network communications such as performed by a network adapter card or network interface controller (NIC). Computers and other devices may be networked together using any one of several available architectures and any one of several corresponding and compatible network protocols. A common network architecture is Ethernet(trademark), such as the 10Base-T Standard operating at 10 Megabits per second (Mbps) and 100Base-TX Ethernet(trademark) Standard operating at 100 Mbps according to the IEEE Standard 802.3. A newer Ethernet(trademark) architecture operating at 1 Gigabit per second (Gbps) is available and becoming more prominent for server systems. The present invention is illustrated using the Ethernet(trademark) architecture and TCP/IP (Transmission Control Protocol/Internet Protocol), which is a common network protocol particularly for the Internet. The present invention, however, is not limited to any particular network protocol or architecture. In fact, although the present invention is illustrated using network type communication systems, it is not limited to network communications and may be applied to any type of subsystem of a computer.
A computer typically includes a bus system with corresponding slots for receiving compatible network adapter expansion cards, such as NICs, for interfacing the computer to a network. Each NIC includes an appropriate connector for interfacing a compatible network cable, such as a coaxial cable, a twisted-wire cable, a fiber optic cable, etc. For example, in an Ethernet(trademark) star configuration, each NIC includes an RJ-45 connector for receiving a compatible RJ-45 plug of a twisted-wire cable, where each network cable is coupled to a central device such as a repeater, hub, switch, etc. The bus system may include one or more of several standard or proprietary buses, such as the Peripheral Component Interconnect (PCI), the Industry Standard Architecture (ISA) bus, the Extended ISA (EISA) bus, the MicroChannel Architecture (MCA) bus, etc., as well as a host bus and an input/output (I/O) extension bus, sometimes called the xe2x80x9cX-busxe2x80x9d. The NIC also includes a compatible connector to plug into a corresponding bus of the host computer system. For example, A PCI compatible NIC including a PCI connector is common for servers.
The primary function of the NIC is to transfer data to and from system memory of the computer system, although the NIC may perform many other network functions. A NIC may have its own processor or processing logic, but many network functions may still require processing by the main processor or central processing unit (CPU) of the host computer system. For example, a NIC often includes Direct Memory Access (DMA) circuitry or the like for transferring data between the NIC and the system memory. After transferring data from the network to the computer system memory, however, the computer CPU may be needed to process the transferred data in the system memory. In a similar manner, when data is transferred from the system memory to the NIC or asserted onto the network, the NIC may inform the CPU that the transfer has completed so that the CPU may perform associated functions or processing.
The NIC asserts an indication or interrupt to inform the host CPU that processing by the CPU associated with a network function is necessary. A certain amount of interrupt latency exists between when the interrupt is asserted and when the host CPU executes a driver associated with the NIC in response to the interrupt to handle network associated processing. The interrupt latency is caused by several factors, such as delay caused by the computer bus system when transferring the interrupt to the appropriate interrupt handling circuitry of the computer. The host CPU may cause further interrupt delays, since it typically must complete any current processing and usually must locate and execute the NIC driver to handle the interrupt.
One or more computers in a network configuration may operate as servers for other computers and devices in the network. Often, the other computers and devices rely on the server(s) for information, storage, access to databases, programs, other networks, etc., and various other services. It is desired to improve network processing between a network adapter or NIC and its host computer for any computer coupled to a network. This is particularly true when the computer operates as a server on the network. It is desired that each server operate as efficiently as possible and to provide as much data bandwidth as possible, especially during periods of heavy demand and increased network traffic. More generally, it is desired to improve the efficiency of processing associated with any type of subsystem of a computer.
A dynamic early indication system according to the present invention includes a processor, subsystem logic that performs a subsystem function to be reported to the processor, an early indicator, indication logic that provides an indication to inform the processor that processing associated with the subsystem function is needed at a completion time of the subsystem function, and a driver that is executed by the processor in the response to the indication to perform the subsystem processing. The indication logic provides the indication prior to the completion time of the subsystem function if the early indicator indicates early indication. Also, the driver, when executed by the processor, controls the early indicator in an attempt to improve efficiency of the subsystem processing.
In one embodiment, a memory is included and coupled to the processor, where the subsystem function is associated with transferring data between the network and the memory of the computer system. In this case, the completion time corresponds to when data has been completely stored in the memory. The indication logic calculates or otherwise estimates the completion time using a known or otherwise determined data transfer rate and the amount of data to be transferred and calculates an early time using the calculated completion time and a predetermined early time offset. In this manner, the indication logic provides the indication at the early time if so indicated by the early indicator, such as before the completion time by an amount of time corresponding to the predetermined early time offset.
The early indicator may be an early logic bit that determines whether early indication is to be used. For example, if the early bit is set, then the indication logic provides the indication before the completion time of the subsystem function. Otherwise, if the early bit is cleared, the indication logic provides the indication when it is determined that the subsystem function has been completed. In one embodiment, the computer is coupled to a network and the subsystem logic comprised network logic. In that case, the driver may include monitoring logic that monitors network traffic and sets the early logic bit during relatively low network traffic. The driver also clears the early logic bit during relatively high network traffic to effectively turn off early indication. In this manner, the driver determines whether early indication is used or not by setting the early logic bit, where the decision is based upon the relative traffic of the network.
In another embodiment, the early indicator is a programmable early time offset. In this case, the indication logic estimates the completion time of the subsystem function and provides the indication at a time based on the estimated completion time and the early time offset. For example, the indication may provide the indication at an early time by subtracting the early time offset from the estimated completion time to provide the indication early. The driver, when executed, may determine a difference time between an actual completion time of the subsystem function and a response time of the driver and accordingly adjust the early time offset in an attempt to reduce subsequent difference times. For example, if the driver is executed too early so that the subsystem function has not completed, then the driver may increase the early time offset so that next time the driver will not be executed too early. If the driver is executed too late or after the subsystem function has completed, then the driver may decrease the early time offset in an attempt to cause the execution of the driver on time.
In embodiments where the early indicator comprises a programmable early time offset, it may require substantial additional logic for the driver to determine the difference time between its execution and the actual completion time of the network function. To eliminate the need for such additional logic, the driver may simply determine whether the subsystem function has been completed and accordingly adjust the early time offset by an incremental amount. In this manner, the early time offset will close in on a maximal efficient value after several iterations of the executed driver. For network embodiments in which the computer is coupled to a network, the size of the incremental amount may depend upon the relative speed of the network. For example, the incremental amount may be several microseconds for a 100 Mbps embodiment or one or two microseconds for a 100 Mbps embodiment or a hundred or so nanoseconds for a one Gigabit per second (Gbps) embodiment.
In yet another embodiment, a timer is provided that is initiated when the indication is provided. The driver reads the timer when executed in response to the indication. In this manner, the timer includes a timing value or count value that represents elapsed time from when the indication is provided to when the driver is executed in response to the indication. For network embodiments, the elapsed time may represent an indication latency that may be used by a network administrator to adjust network operating parameters to improve efficiency. Alternatively, if the early indicator is a programmable early time offset, the driver may adjust the early time offset using the latency value read from the timer.
A computer system according to other embodiments of the present invention includes at least one peripheral bus, a disk drive and corresponding disk drive controller, a processor, a system memory, an expansion card coupled to the peripheral bus including subsystem logic that performs a predetermined function, and a subsystem driver that is executed by the processor from system memory in response to an interrupt from the subsystem card to perform subsystem processing associated with the predetermined function. The expansion card includes the subsystem logic, an early indicator that indicates an early interrupt mode of operation and interrupt logic that asserts the interrupt to inform the processor that subsystem processing associated with the subsystem function is needed at its completion time. The subsystem driver, when executed by the processor, controls the early indicator in an attempt to improve efficiency of subsequent processing associated with the predetermined function.
In a more specific embodiment, the computer system includes at least one peripheral bus, a disk drive and corresponding disk drive controller, a processor, a system memory, a network interface card (NIC) coupled to the peripheral bus including network logic that performs a network function, and a NIC driver that is executed by the processor from system memory in response to a network interrupt from the NIC to perform network processing associated with the network function. The NIC also includes an early indicator that indicates an early interrupt mode of operation and interrupt logic that asserts the network interrupt to inform the processor that network processing associated with the network function is needed at a completion time of the network function. The NIC driver, when executed by the processor, controls the early indicator in an attempt to improve efficiency of network processing.
In other embodiments, the completion time corresponds to when a group of data from the NIC is completely transferred to and stored in the system memory. The interrupt logic may further include timing logic that calculates the completion time based on the data transfer rate from the NIC to the system memory and an amount of data to be transferred. The timing logic calculates an early interrupt time using the calculated completion time and a predetermined early time offset. The interrupt logic asserts the network interrupt at the early interrupt time if the early indicator indicates the early interrupt mode of operation.
The early indicator may be an early logic bit that indicates the early interrupt mode when set. In one embodiment, the subsystem logic performs a predetermined function associated with data communication. The subsystem driver includes monitor logic that monitors data communication of the subsystem logic, where the subsystem driver sets the early logic bit during relatively low communication traffic and clears the early logic bit during relatively high communication traffic. For a network embodiment, the NIC driver may include monitor logic that monitors network traffic, where the NIC driver sets the early logic bit during relatively low network traffic and clears the early logic bit during relatively high network traffic.
Alternatively, the early indicator is a programmable early time offset. The interrupt logic includes timing logic that calculates a completion time and that determines an early interrupt time based on the difference between the calculated completion time and the early time offset. The subsystem driver may further include timing logic that determines a difference time between actual completion time of the subsystem function and a response time of the subsystem driver when executed by the processor. The subsystem driver may include interrupt logic that adjusts the early time offset in an attempt to reduce subsequent difference times.
In yet another embodiment, the subsystem driver interrupt logic, when executed, simply determines whether the subsystem function is completed and adjusts the early time offset by a predetermined incremental amount. The embodiment of adjusting the early time offset by an incremental amount allows for a simpler and more efficient design.
In another embodiment, the expansion card includes a counter that is started when the interrupt is asserted. The subsystem driver includes interrupt logic that reads a count value from the counter when the subsystem driver is executed in response to the interrupt. The count value read from the counter may be used to adjust the early indicator if it comprises a programmable early time offset.
A network controller system according to the present invention, for a computer coupled to a network, includes a processor, network logic that performs a network function, an early indicator, indication logic that provides an indication to inform the processor that network processing associated with the network function is needed at a completion time of the network function, and a driver that is executed by the processor in the response to the indication to perform the network processing. The indication logic provides the indication prior to the completion time of the network function if the early indicator indicates early indication. Also, the driver, when executed by the processor, controls the early indicator in an attempt to improve efficiency of the network processing.
A method of providing dynamic early indications for a subsystem of a computer includes providing an early value indicative of early interrupt mode of operation, initiating a subsystem function and providing an indication to request processing associated with the subsystem function. The indication is provided before the subsystem function is completed if the early value indicates the early interrupt mode of operation. The method further includes executing a driver to perform the processing associated with the subsystem function in response to the indication, where the executing driver controls the early value in an attempt improve efficiency of processing associated with the subsystem function.
A method of providing early indications for a computer coupled to a network includes providing an early value indicative of early indication mode of operation, initiating a network function and providing an indication to request network processing associated with the network function. The indication is provided before the network function is completed if the early value indicates the early indication mode of operation. The method further includes executing a driver to perform the network processing associated with the network function in response to the indication, where the executing driver controls the early value in an attempt improve efficiency of network processing.
The subsystem function may be any one or more of many possible functions, such as transferring data to a memory of the computer. For data transfer to the computer, the method further includes calculating an estimated completion time of when data is completely transferred to the memory, calculating an early time using the estimated completion time in a predetermined early time offset, and providing the indication at the early time if the early value indicates the early indication mode of operation.
The subsystem function may be associated with data communication and the early value may comprise an early logic bit, where the method includes monitoring communication data flow, setting the early logic bit during relatively low data flow, and clearing the early logic bit during relatively high data flow. For network embodiments in which the computer is coupled to a network, the method may include monitoring traffic on the network, setting the early logic bit during relatively low network traffic and clearing the early logic bit during relatively high. network traffic.
Alternatively, the early value comprises a programmable early time offset, where the method includes calculating an estimated completion time of the subsystem function and providing the indication before the subsystem function is completed using the estimated completion time and the early time offset. The method may further include determining a difference time between an actual completion time of the subsystem function and when the driver is executed to perform the processing associated with the subsystem function and adjusting the early time offset in an attempt to reduce subsequent difference times. Alternatively, the method comprises determining whether the subsystem function is completed when the driver is executed and adjusting the early time offset by an incremental amount. For example, the early time offset may be decreased by the incremental amount if the subsystem function has completed or the early time offset is increased if the subsystem function has not completed.
The method may further comprise starting a counter when the indication is provided and reading a count value from the counter by the driver when executed in response to the indication. The method may further comprise determining an estimated completion time of the subsystem function and providing an indication before the estimated completion time by an amount of time corresponding to the early time offset and adjusting early time offset using the count value.
It is now appreciated that a dynamic early indication system according to the present invention improves subsystem processing between a computer subsystem and its host processor by substantially reducing or otherwise eliminating indication or interrupt latency. For network embodiments, the present invention improves network processing between a network adapter or NIC and its host computer by substantially reducing or otherwise eliminating interrupt latency. In the configuration in which the early indicator is an early bit, a predetermined early time offset is used by the subsystem to assert interrupts early, where the early time offset is effectively an estimate of interrupt latency. The early time offset may be a best estimate value, a measured value or a calculated value based on a particular subsystem configuration. The early time offset may be fixed or programmable. In general, the driver is called to service the interrupt closer to when processing is actually needed. For configurations in which the early indicator is a programmable time value, the driver continuously and/or periodically adjusts the time value for more accurate results. The incremental adjust method enables a simple yet very effective design since the time value quickly converges on the interrupt latency, and then is continuously adjusted to closely track the interrupt latency.
A network controller system with dynamic early interrupts according to the present invention is particularly useful on network server systems. Data flow between the network adapter and host computer memory is processed much more quickly, thereby significantly increasing bandwidth and improving network traffic flow.